Referring to FIG. 1, a cross sectional perspective view of a striped trench metal-oxide-semiconductor field effect transistor (TMOSFET) 100 according to the conventional art is shown. The striped TMOSFET 100 comprises a plurality of source contacts 110, a plurality of source regions 115, a plurality of gate regions 120, a plurality of gate insulator regions 125, a plurality of body regions 130, a drain region 135, 140 and drain contact 145. The drain region 135, 140 may optionally include a first drain portion 140 and a second drain portion 135.
The body regions 130 are disposed above the drain region 135, 140. The source regions 115, gate regions 120 and the gate insulator regions 125 are disposed within the body regions 130. The gate regions 120 and the gate insulator regions 125 are formed as parallel-elongated structures. The gate insulator region 125 surrounds the gate region 120. Thus, the gate regions 120 are electrically isolated from the surrounding regions by the gate insulator regions 125. The gate regions 120 are coupled to form a common gate of the device 100. The source regions 115 are formed as parallel-elongated structures along the periphery of the gate insulator regions 125. The source regions 115 are coupled to form a common source of the device 100, by the source contacts 110. Although shown as a plurality of individual source contacts 110, it is appreciated that the source contacts 110 may be implemented as a single conductive layer coupling all the source regions 1115. The source contacts 110 also couple the source regions 115 to the body regions 130.
The source regions 115 and the drain region 140 are heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous or arsenic. The body regions 130 are p-doped (P) semiconductor, such as silicon doped with boron. The gate region 120 is heavily n-doped (N+) semiconductor, such as polysilicon doped with phosphorous. The gate insulator regions 125 may be an insulator, such as silicon dioxide.
When the potential of the gate regions 120, with respect to the source regions 115, is increased above the threshold voltage of the device 100, a conducting channel is induced in the body region 130 along the periphery of the gate insulator regions 125. The striped TMSOFET 100 will then conduct current between the drain region 140 and the source regions 115. Accordingly, the device is in its on state.
When the potential of the gate regions 120 is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region 140 and the source regions 115 will not cause current to flow there between. Accordingly, the device 100 is in its off state and the junction formed by the body region 130 and the drain region 140 supports the voltage applied across the source and drain.
If the drain region 135, 140 comprises a second drain portion 135 disposed above a first drain portion 140, the second portion of the drain region 135 is lightly n-doped (N−) semiconductor, such as silicon doped with phosphorous or arsenic, and the first portion of the drain region 140 is heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous or arsenic. The lightly n-doped (N−) second portion of the drain region 135 results in a depletion region that extends into both the body regions 130 and the second portion of the drain region 135, thereby reducing the punch through effect. Accordingly, the lightly n-doped (N−) second portion of the drain region 135 acts to increase the breakdown voltage of the striped TMOSFET 100.
The channel width of the striped TMOSFET 100 is a function of the width of the plurality of the source regions 115. Thus, the striped TMOSFET 100 provides a large channel width to length ratio. Therefore, the striped TMOSFET may advantageously be utilized for power MOSFET applications, such as switching elements in a pulse width modulation (PWM) voltage regulator.
Referring to FIG. 2, a cross sectional perspective view of a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) 200 according to the conventional art is shown. The closed cell TMOSFET 200 comprises a plurality of source contacts 210, a plurality of source regions 215, a gate region 220, a gate insulator region 225, a plurality of body regions 230, a drain region 235, 240 and a drain contact 245. The drain region 235, 240 may optionally include a first drain portion 240 and a second drain portion 235.
The body regions 230, the source regions 215, the gate region 220 and the gate insulator region 225 are disposed above the drain region 235, 240. A first portion of the gate region 220 and the gate insulator region 225 is formed as substantially parallel-elongated structures 221. A second portion of the gate region 220 and the gate insulation region 225 is formed as substantially normal-to-parallel elongated structures 222. The first and second portions of the gate region 220 are all interconnected and form a plurality of cells. The body regions 230 are disposed within the plurality of cells formed by the gate region 220.
The gate insulator region 225 surrounds the gate region 220. Thus, the gate region 220 is electrically isolated from the surrounding regions by the gate insulator region 225. The source regions 215 are formed in the plurality of cells, along the periphery of the gate insulator region 225.
The source regions 215 are coupled to form a common source of the device 200, by the source contacts 210. Although shown as a plurality of individual source contacts 210, it is appreciated that the source contacts 210 may be implemented as a plurality of conductive strips each coupling a plurality of source regions 215, a single conductive layer coupling all the source regions 215, or the like. The source contacts 210 also couple the source regions 215 to the body regions 230.
The source regions 215 and the drain region 240 are heavily n-doped (+N) semiconductor, such as silicon doped with phosphorous or arsenic. The body regions 230 are p-doped (P) semiconductor, such as silicon doped with boron. The gate region 220 is heavily n-doped semiconductor (N+), such as polysilicon doped with phosphorous. The gate insulator region 225 may be an insulator, such as silicon dioxide.
When the potential of the gate region 220, with respect to the source regions 215, is increased above the threshold voltage of the device 200, a conducting channel is induced in the body region 230 along the periphery of the gate insulator region 225. The device 200 will then conduct current between the drain region 240 and the source regions 215. Accordingly, the device 200 is in its on state.
When the potential of the gate region 220 is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region 240 and the source regions 215 will not cause current to flow there between. Accordingly, the device is in its off state and the function formed by the body region 230 and the drain region 240 supports the voltage applied across the source and drain.
If the drain region 235, 240 comprises a second portion 235 disposed above a second portion 240, the second portion of the drain region 235 is lightly n-doped (N−) semiconductor, such as silicon doped with phosphorous or arsenic, and the first portion of the drain region 240 is heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous. The lightly n-doped (N−) second portion of the drain region 235 results in a depletion region that extends into both the body regions 230 and the second portion of the drain region 235, thereby reducing the punch through effect. Accordingly, the lightly n-doped (N−) second portion of the drain region 235 acts to increase the breakdown voltage of the closed cell TMOSFET 200.
The channel width of the closed cell TMOSFET 200 is a function of the sum of the width of the source regions 215. Thus, the closed cell TMOSFET 200 geometry advantageously increases the width of the channel region, as compared to the striped TMOSFET 100. Accordingly, the closed cell TMSOFET 200 has a relatively low channel resistance (e.g., on resistance), as compared to the striped TMOSFET 100 geometry. The low channel resistance reduces power dissipated in the closed cell TMOSFET 200, as compared to the striped TMOSFET 100.
Similarly, the gate-to-drain capacitance of the closed cell TMOSFET 220 is a function of the area of overlap between the bottom of the gate region 220 and the drain region 240. Accordingly, the closed cell TMOSFET 200 geometry suffers from a higher gate-to-drain capacitance, as compared to the striped TMOSFET 100. The relatively high gate to drain capacitance limits the switching speed of the closed cell TMOSFET 200, as compared to the striped TMOSFET 100.